1. Field of the Invention
The present invention relates to printers. More particularly, the present invention relates to ink jet printers.
2. General Background of the Invention
One of the primary goals when designing inkjet heater chips is to create a product that will reduce the overall cost of the finished print head assembly and where possible the printer itself. One method that meets these goals is to reduce the number of I/O pads required by the chip. By reducing the number of I/Os the following benefits can be realized:    1.) The tab circuit size can be reduced.    2.) The number of interconnects between print head, tab circuit and printer carrier card can be reduced.    3.) More chip area can be used for integrated circuits.    4.) The potential for EMR from the printhead flex cable is reduced.
Present Lexmark serially loaded printheads require at a minimum a data input signal, a clock input signal and a load input signal.
The following patent documents, and all patents and patent documents mentioned herein, are incorporated herein by reference:    U.S. Pat. Nos. 6,076,922; 6,027,195; 5,940,608; 5,838,339; 5,790,140; 4,963,885; Japanese patent document nos.: JP 8034137; JP 63137848; JP 5031898; and JP 198202; European publication no. EP 0 749 089 A2.
U.S. Pat. No. 6,076,922 to Knierim describes a method and apparatus for generating a dot clock signal for controlling operation of a print head. The system is for a printer that includes an image transfer drum and a printhead for ejecting drops of ink toward the image transfer drum. A control mechanism controls operation of the printhead. The control mechanism includes a position encoder that generates an encoder signal and a digital phase locked loop circuit that receives the encoder signal and generates the dot clock signal. Firing of the print head is controlled by the dot clock signal. Knierim appears to disclose an off carrier circuit for generating a firing clock based upon readings of an encoder strip.
U.S. Pat. No. 5,940,608 to Manning describes a clock generator circuit for an integrated circuit that includes a phase detector for comparing the phase of a delayed external clock signal to the phase of an internal clock signal. An error signal corresponding to the difference in phase between the two clock signals is applied to a differential amplifier where the error signal is offset by a value corresponding to the delay of an external clock signal. The offset error signal is applied to the control input of a voltage controlled oscillator which generates the internal clock signal.
U.S. Pat. No. 5,790,140 to Koizumi et al. describes a printing head that resets the count value of a counter in response to an externally supplied signal. This externally supplied signal is described as a clock signal supplied from the head driver. The decoder generates a selection signal in accordance with the count value and selects a divided heat-generating element group. An electric current is then supplied to heat-generating resistors in the selected group to perform a printing operation. According to the '140 patent, the printer can thus be controlled by a smaller number of control signals.
Our Lexmark U.S. Pat. No. 6,547,356 describes creating a second clock for latching serial data in a heater chip. The second clock moves the data from an internal shift register to internal latches on a heater chip. The second clock is created from an extra bit in the data shift register. The extra bit is used as a trigger for the second clock. After a predetermined delay occurs from when the data is completely shifted in, the extra bit in the shift register, when enabled, triggers the second clock to occur and move the data from the shift register to latches.